Talks
2026
How Secure Are Commercial RISC-V CPUs?
2025
No Clock, No Problem: Discovering Timer-Free Cache-State Side Channels
When Timers Fail: Discovering Hidden Cache State Leaks on ARM CPUs
2024
From Rowhammer to GhostWrite: Advanced Exploitation and Discovery of Hardware Bugs
Arbitrary Data Manipulation and Leakage with CPU Zero-Day Bugs on RISC-V